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1 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 16m-bit [2m x 8/1m x 16] cmos otp rom general description the mx27c1610 is a 16m-bit, one time programmable read only memory. it is organized as 2m x 8 or 1m x 16 and has a static standby mode, and features fast programming. for programming outside from the sys- tem, existing eprom programmers may be used. the mx27c1610 supports a intelligent fast programming al- gorithm which can result in programming time of less than two minutes. this one time programmable read only memory is packaged in industry standard 42 pin dual-in-line plas- tic package. pin configurations pdip pin description symbol pin name a0~a19 address input q0~q14 data input/output ce chip enable input oe output enable input byte/vpp word/byte selection /program supply voltage q15/a-1 q15(word mode)/lsb addr. (byte mode) vcc power supply pin (+5v) gnd ground pin block diagram preliminary features ? 2m x 8 or 1m x 16 organization ? 5v vcc for read operation ? 10v vpp programming operation ? fast access time: 100/120 ns ? totally static operation ? completely ttl compatible ? operating current: 60ma ? standby current: 100ua ? package type: - 42 pin plastic dip control logic output buffers q0~q14 q15/a-1 ce oe byte/vpp a0~a19 address inputs y-decoder x-decoder y-decoder 16m bit cell maxtrix vcc vss . . . . . . . . . . . . . . . . mx27c1610 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte/vpp gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc
2 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 word mode(byte = vcc) ce oe q15/a-1 mode q0-q7 supply current h x high z non selected high z standby(icc2) l h high z non selected high z operating(icc1) l l dout selected dout operating(icc1) note : x = h or l truth table of byte function byte mode(byte = gnd) ce oe q15/a-1 mode q0-q7 supply current h x x non selected high z standby(icc2) l h x non selected high z operating(icc1) l l a-1 input selected dout operating(icc1) functional description read mode the mx27c1610 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. as- suming that addresses are stable, address access time (tacc) is equal to the delay from ce to output (tce). data is available at the outputs toe after the falling edge of oe's, assuming that ce has been low and ad- dresses have been stable for at least tacc - t oe. word-wide mode with byte/vpp at vcc 0.2v outputs q0-7 present data q0-7 and outputs q8-15 present data q8-15, after ce and oe are appropriately enabled. byte-wide mode with byte/vpp at gnd 0.2v, outputs q8-15 are tri- stated. if q15/a-1 = vih, outputs q0-7 present data bits q8-15. if q15/a-1 = vil, outputs q0-7 present data bits q0-7. standby mode the mx27c1610 has a cmos standby mode which re- duces the maximum vcc current to 100 ua. it is placed in cmos standby when ce is at vcc 0.2v. the mx27c1610 also has a ttl-standby mode which re- duces the maximum vcc current to 4 ma. it is placed in ttl-standby when ce is at vih. when in standby mode, the outputs are in a high-impedance state, inde- pendent of the oe input. two-line output control function to accommodate multiple memory connections, a two- line control function is provided to allow for: 1. low memory power dissipation, 2. assurance that output bus contention will not occur. it is recommended that ce be decoded and used as the primary device-selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the out- put pins are only active when data is desired from a particular memory device.
3 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 system considerations during the switch between active and standby condi- tions, transient current peaks are produced on the ris- ing and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. at a minimum, a 0.1 uf ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and gnd to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on one time programmable read only memory arrays, a 4.7 uf bulk electrolytic capacitor should be used between vcc and gnd for each eight devices. the location of the capacitor should be close to where the power supply is connected to the array. write operations commands are written to the command interface register (cir) using standard microprocessor write timings. the cir serves as the interface between the microprocessor and the internal chip operation. the cir can decipher read array, read silicon id and pro- gram command. in the event of a read command, the cir simply points the read path at either the array or the silicon id, depending on the specific read command given. for a program cycle, the cir informs the write state machine, and the write state machine and the write state machine will control the program sequences and the cir will only respond to status reads. after the write state machine has completed its task, it will allow the cir to respond to its full command set. the cir stays at read status register mode until the microproc- essor issues another valid command sequence. device operations are selected by writing commands into the cir. see command definition table below. mode select table byte/ mode ce oe a9 a0 q15/a-1 vpp(5) q8-14 q0-7 read (word) (2) vil vil x x q15 out vih q8-14 out q0-7 out read (upper byte) (2) vil vil x x vih vil high z q8-15 out read (lower byte) (2) vil vil x x vil vil high z q0-7 out output disable (2) vil vih x x high z x high z high z standby (2) vih x x x high z x high z high z write operation (2) vil vih x x q15 in vpp q8-14 in q0-7 in manufacturerid(3)(1) vil vil vh vil 0b vih 00h c2h device id(3)(1) vil vil vh vih 0b vih 00h 6ah notes: 1. vh = 10v 0.5v 2. x either vil or vih. 3. a1= vil, other address lines not specified are at "x" states 4. see dc programming characteristics for vpp voltages. 5. byte/vpp is intended for operation under dc voltage conditions only. vpp=10v 0.5v for write operation
4 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 command read/ silicon page/byte read clear sequence reset id read program status reg. status reg. bus write 4 4 4 4 3 cycles req'd first bus addr 5555h 5555h 5555h 5555h 5555h write cycle data aah aah aah aah aah second bus addr 2aaah 2aaah 2aaah 2aaah 2aaah write cycle data 55h 55h 55h 55h 55h third bus addr 5555h 5555h 5555h 5555h 5555h write cycle data f0h 90h a0h 70h 50h fourth bus addr ra 00h/01h pa x read/write cycle data rd c2h/6ah pd srd command definitions of write operation table notes : 1. in the write operation mode, byte/vpp should be set to 10v 0 .5v. 2. 5555h and 2aaah address command codes stand for hex number starting from a0 to a14. 3. ra=address of the memory location to be read. rd=data read from location ra during read operation. pa=address of the memory location to be programmed. po=data to be programmed at location pa. device operation silicon id read the silicon id read mode allows the reading out of a binary code from the device and will identify its manu- facturer and type. this mode is intended for use by programming equipment for the purpose of automati- cally matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the de- vice. mx27c1610 silion id codes type a 19 a 18 a 17 a 16 a 1 a 0 code(hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer code** x x x x vil vil c2h* 1 1 0 0 0 0 1 0 device code** x x x x vil vih 6ah* 0 1 1 0 1 0 1 0 * the high byte of the code will be 00h and low byte of the code will be c2h for manufacturer code and 6ah of device code. ** all other address lines not specified are also at "x" state. x=vih or vil. to activate this mode, the programming equipment must force vid (10v o.5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from vil to vih. all addresses are don't cares except a0 and a1. the manufacturer and device codes may also be read via the command register, for instances when the mx27c1610 is programmed in a system without access to high voltage on the a9 pin.
5 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the cir contents are altered by a valid command sequence. the device will automatically power-up in the read/re- set state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. the mx27c1610 is accessed when ce and oe are low the data stored at the memory location determined by the address pins is asserted on the outputs. the out- puts are put in the high impedance state whenever ce or oe is high. this dual line control gives designers flexibility in preventing bus contention. note that the read/reset command is not valid when pro- gram is in progress. page program the device is set up in the programming mode when the programming voltage vpp=10v is applied with vcc=5v, and oe=vih. any attempt to write to the device without the three- cycle command sequence will not start the internal write state machine(wsm), no data will be written to the de- vice. after three-cycle command (see command table) se- quence is given, a word load is performed by applying a low pulse on the ce input with ce low and oe high. the address is latched on the falling edge of ce the data is latched by the rising edge of ce . maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program sec- tion below. word-wide load word loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. a word load is performed by applying a low pulse on the ce input with ce and oe high. the address is latched on the falling edge of ce. the data is latched by the rising edge of ce. program the device is programmed on a page basis. once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal pro- gramming period. after the first data word has been loaded into the device, successive words are entered in the same manner. the time between word loads must be less than 30us otherwise the load period could be teminated. a6 to a19 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. the page address must be valid dur- ing each high to low transition of ce. a0 to a5 specify the word address withih the page. the word may be loaded in any order; sequential loading is not required. if a high to low transition of ce is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. the auto page program terminates when status on q7 is "1" at which time the device stays at read status reg- ister mode until the cir contents are altered by a valid command sequence.
6 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 read status register the mxic's16 mbit otp rom contains a status regis- ter which may be read to determine when a program operation is complete, and whether that operation com- pleted successfully. the status register may be read at any time by writing the read status command to the cir. after writing this command, all subsequent read operations output data from the status register until an- other valid command sequence is written to the cir. a read array command must be written to the cir to re- turn to the read array mode. it should be noted that the contents of the status regis- ter are latched on the falling edge of oe or ce which- ever occurs last in the read cycle. this prevents pos- sible bus errors which might occur if the contents of the status register change while reading the status register. ce or oe must be toggled with each subsequent status read, or the completion of a program operation will not be evident. the status register is the interface between the micro- processor and the write state machine (wsm). when the wsm is active, this register will indicate the status of the wsm, and will also hold the bits indicating whether or not the wsm was successful in performing the de- sired operation. the wsm can set status bit4 and bit7. however, the wsm can only clear bit 7 but can not clear bit 4. if program fail status bit is detected, the status register is not cleared until the "clear status register command" is issued. the mx27c1610 automatically out- puts status register data when read after page pro- gram or read status command write cycle. the inter- nal state machine is set for reading array data upon device power-up. clear status register the program fail status bit (q4) are set by the write state machine, and can only be reset by the system software. these bits can indicate various failure conditions(see table below). by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages . the status register may then be read to determine if an error occurred during that programming series. this adds flexibility to the way the device may be programmed. additionally, once the program fail bit happens, the program operation can not be performed further. the program fail bit must be reset by system software before further page program are attempted. to clear the status register, the clear status register command is written to the cir. then, any other command may be issued to the cir. note again that before a read cycle can be initiated, a read command must be written to the cir to specify whether the read data is to come from the array, status register or silicon id.
7 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 notes: 1. q7 : write state machine status 1 = ready, 0 = busy q4 : program fail status 1 = fail in program, 0 = successful program q3=0 = reserved for future enhancements. these bits are reserved for future use ; mask them out when polling the status register. 2. program status is for the status during page programming. 3. fail status bit(q4) is provied during page program mode. status register table low vcc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for vcc less than vlko(= 3.2v , typically 3.5v). if vcc < vlko, the command register is disabled and all internal pro- gram circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the vcc level is greater than vlko. it is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when vcc is above vlko. write pulse "glitch" protection noise pulses of less than 10ns (typical) on ce will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil,ce = vih. to initiate a write cycle ce must be a logical zero while oe is a logical one, and byte/vpp=10v. status notes q7 q4 q3 in progress program 1,2 0 0 0 complete program 1,2 1 0 0 fail program 1,3 1 1 0 after clearing status register 10 0 notice: stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is stress rating only and functional operational sections of this specification is not implied. exposure to ab- solute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are sub- ject to change. electrical specifications absolute maximum ratings rating value ambient operating temperature 0 c to 70 c storage temperature -65 c to 125 c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 -0.5v to 13.5v byte/vpp -0.5v to 12.0v
8 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 switching test waveforms switching test circuits capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 14 pf vin = 0v cvpp vpp capacitance 20 pf vpp=0v cout output capacitance 16 pf vout = 0v device under test diodes = in3064 or equivalent cl = 100 pf including jig capacitance 1.2k ohm 1.6k ohm +5v cl 2.0v 0.8v 2.4v 0.45v test points input 2.0v 0.8v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are < 10ns.
9 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 dc characteristics ta = 0 c to 70 c, vcc = 5v 10% symbol parameter notes min. typ. max. units test conditions ili input leakage 1 10 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 10 ua vcc = vcc max current vin = vcc or gnd isb1 vcc standby 1 1 100 ua vcc = vcc max current(cmos) ce = vcc 0.2v isb2 vcc standby 2 4 ma vcc = vcc max current(ttl) ce = vih icc1 vcc read 1 50 60 ma vcc = vcc max current cmos: ce = gnd 0.2v byte/vpp = gnd 0.2v or vcc 0.2v inputs = gnd 0.2v or vcc 0.2v ttl : ce = vil, byte/vpp = vil or vih inputs = vil or vih, f = 10mhz, iout = 0 ma icc2 vcc read 1 30 35 ma vcc = vcc max, current cmos: ce = gnd 0.2v byte/vpp = vcc 0.2v or gnd 0.2v inputs = gnd 0.2v or vcc 0.2v ttl: ce= vil, byte/vpp = vih or vil inputs = vil or vih, f = 5mhz, iout = 0ma icc4 vcc program 1 30 50 ma program in progress current vil input low voltage 2 -0.3 0.8 v vih input high voltage 3 2.4 vcc+0.3 v vol output low voltage 0.45 v iol = 2.1ma voh output high voltage 2.4 v ioh = -2ma notes: 1. all currents are in rms unless otherwise noted. typical values at vcc = 5.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. vil min. = -1.0v for pulse width 50ns. vil min. = -2.0v for pulse width 20ns. 3. vih max. = vcc + 1.5v for pulse width 20ns. if vih is over the specified maximum value, read operation cannot be guaranteed.
10 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 ac characteristics --- read operations 27C1610-10 27c1610-12 symbol descriptions min. max. min. max. unit conditions tacc address to output delay 100 120 ns ce=oe=vil tce ce to output delay 100 120 ns oe=vil toe oe to output delay 50 50 ns ce=vil tdf oe high to output in high z 0 35 0 35 ns ce=vil toh address to output hold 0 0 ns ce=oe=vil tbacc byte/vpp to output delay 100 120 ns ce= oe=vil tbhz byte/vpp low to output in high z 50 50 ns ce=vil test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times: 10ns ? output load: 1ttl gate+100pf(including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
11 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 figure 1. read timing waveforms addresses tacc tce tdf toh toe addresses stable data out valid vcc 5.0v gnd data out ce oe power-up standby device and address selection outputs enabled data valid standby power-down vcc vih vil vih vil vih vil voh vol high z high z note: vcc 1.for real world application, byte/vpp pin should be either static high(word mode) or static low(byte mode); dynamic switching of byte/vpp pin is not recommended.
12 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 figure 2. byte/vpp timing waveforms addresses tacc tce tdf toh data output toe addresses stable data(q0-q7) ce oe byte vih vil vih vil vih vil vih vil voh vol voh vol high z high z data output data output high z tbacc high z tbhz data(q8-q15)
13 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 ac characteristics --- program operations 27C1610-10 27c1610-12 symbol description min. max. min. max. unit twc write cycle time 100 120 ns tas address setup time 0 0 ns tah address hold time 50 60 ns tds data setup time 50 60 ns tdh data hold time 0 0 ns toes output enable setup time 0 0 ns tces ce setup time 0 0 ns tcs ce setup time 0 0 ns tch ce hold time 0 0 ns twp write pulse width 50 60 ns twph write pulse width high 30 50 ns tbalc word address load cycle 0.3 30 0.3 30 us tbal word address load time 100 100 us tsra status register access time 70 90 ns tcesr ce setup before s.r. read 70 70 ns tvcs vcc setup time 50 50 us traw read operation set up time after write 20 20 us
14 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 figure 3. command write timing waveforms tas toes tds tah din tdh valid addresses ce oe data high z (q0~q15) vcc tcs tvcs note: 1.byte/vpp pin should be static at 10v+0.5v during write operation. 2.byte/vpp pin should be static at ttl, or cmos level, during read operation. vih vil 10v byte/vpp
15 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 figure 4. automatic page program timing waveforms tas tds tah tdh tbalc a15~a19 ce oe data twc aah 55h a0h srd 55h 55h aah 2ah 55h 55h word offset address page address page address a6~a14 a0~a5 tbal tces tsra write data note: 1.byte/vpp should be static at 10v+0.5v during page programming last word offset address last write data vih q0~q15 2.before oe going low to "read mode", byte/vpp must from vh(10v) to vih or vil vih vil 10v byte/vpp vil twp traw
16 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 programming performance limits parameter min. typ. max. units page programming time 0.9 27 ms chip programming time 14 150 sec byte program time 7 us latchup characteristics min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time.
17 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 package information
18 p/n:pm0593 rev. 1.4, nov. 19, 2002 mx27c1610 revision history revision no. description page date 1.3 changed title from "advanced information" to "preliminary" p1 apr/26/2000 1.4 to modify package information p17 nov/19/2002
19 mx27c1610 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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